On May 8, 2024, Trina Solar Co., Ltd. (“Trina Solar”) and Trina Solar (U.S.), Inc. sued Runergy USA Inc. and Runergy Alabama Inc. in the United States District Court for the District of Delaware. Trina Solar Co., Ltd. v. Runergy USA Inc., Case No. 1:24-cv-00557-JCG, Dkt. No. 1 (D. Del. May 8, 2024). The Trina Solar plaintiffs alleged infringement of U.S. Patent Numbers 9,722,104 (“the ’104 patent”) and 10,230,009 (“the ’009 patent”).
This is one of at least three lawsuits that Trina Solar filed in 2024. On September 10, 2024, Trina Solar sued Jiangsu Runergy New Energy Technology Co., Ltd. in the United States District Court for the Central District of California, Trina Solar Co., Ltd. v. Jiangsu Runergy New Energy Technology Co., Ltd., Case No. 2:24-cv-07694-MSC-MAR, Dkt. No. 1 (C.D. Cal. Sept. 10, 2024), and a month later, Trina Solar sued Canadian Solar (USA) Inc., Canadian Solar US Module Manufacturing Corporation, and Recurrent Energy Development Holdings, LLC in the United States District Court for the District of Delaware, Trina Solar Co., Ltd. v. Candian Solar (USA) Inc., Case No. 1:24-cv-01115-UNA, Dkt. No. 1 (D. Del. Oct. 8, 2024). All three lawsuits allege infringement of the ’104 patent and the ’009 patent.
Notably, on October 3, 2024, the Runergy Defendants petitioned for inter partes review of the ’009 patent. Runergy USA Inc. v. Trina Solar Co., Ltd., IPR 2025-00006, Paper 1 (PTAB Oct. 3, 2024). On the following day, the Runergy Defendants petitioned for inter partes review of the ’104 patent. Runergy USA Inc. v. Trina Solar Co., Ltd., IPR 2025-00007, Paper 1 (PTAB Oct. 4, 2024).
The two Trina Solar patents disclose a solar cell that uses an isolation portion and a tunnel layer to, according to the patents, improve efficiency. Details below.
The ’104 Patent
The ’104 patent, titled “Solar Cell and Method for Manufacturing the Same,” discloses a solar cell that uses a semiconductor substrate sandwiched between two conductive type semiconductor regions and two passivation films. The ’104 patent at 6:39-45. Below is the first embodiment:
The ’104 patent, Fig. 1 (annotated).
As shown above, in the middle of the solar cell is a semiconductor substrate 100. According to the ’104 patent, the solar cell has excellent electrical characteristics because the semiconductor substrate 100 is made of a single crystal semiconductor that has high crystallizability and therefore less defects. The ’104 patent at 6:55-59. The front and/or back surface of the semiconductor substrate 100 may be textured or have concave-convex portions to reduce light reflection and minimize optical loss. Id. at 6:64-7:16.
Also shown above are two passivation films 190A, 190B brought into contact with, and formed on, the first and second conductive type semiconductor regions 120, 170. This mechanism, according to the ’104 patent, immobilizes defects in the semiconductor regions and removes the recombination sites of minority carriers, and in turn, increases the open voltage Voc of the solar cell. The ’104 patent at 11:12-21.
As further shown in Figure 1, an anti-reflection layer 130 may be placed on the second passivation film 190B. According to the ’104 patent, the anti-reflection layer 130 can reduce light reflection on the front surface of the semiconductor substrate 100, thereby improving the efficiency of the solar cell by increasing the amount of light reaching the base region 110 and the first conductive type semiconductor region 170. The ’104 patent at 11:19-32.
The ’104 patent further discloses that the semiconductor substrate 100 includes a base region 110 sitting between two conductive type semiconductor regions 120, 170. A tunnel layer 160 lies between the base region 110 and the first conductive type semiconductor region 170:
The ’104 patent, Fig. 2 (annotated).
According to the ’104 patent, the tunnel layer 160 functions as a barrier for electrons and holes such that minority carriers may not pass, but majority carriers having energy above a specific level may pass. The ’104 patent at 7:60-67. The tunnel layer 160 also functions as a diffusion barrier for preventing the dopant of the first conductive type semiconductor region 170 from being diffused into the semiconductor substrate 100. Id. at 8:3-6.
The ’104 patent also notes that, by spacing the first conductive type semiconductor region 170 and the semiconductor substrate 100 apart using the tunnel layer 160, the open voltage Voc of the solar cell can be further improved. The ’104 patent at 8:56-64. Moreover, the thermal damage to the semiconductor substrate 100 is minimized during manufacturing when the first conductive type semiconductor region 170 is formed outside of the semiconductor substrate 100. Id. at 8:65-9:8.
The ’104 patent suggests additional spacing between the tunnel layer 160 and the first conductive type semiconductor region 170. As shown in Figure 2, this spacing is the isolation portion I at a first distance of D1. The isolation portion I may block contact between the two conductive type semiconductor region 120, 170 in any of the surfaces of semiconductor substrate 100. The ’104 patent at 13:16-23. This would prevent unwanted short-circuit due to impurities from the second conductive type semiconductor region 120 being diffused into the first conductive type semiconductor region 170 via the side or edge of the semiconductor substrate 100. Id. at 13:24-35.
Further, the first passivation film 190A may cover the isolation portion I to prevent deterioration of passivation. This simplifies the manufacturing process because a separate film to protect the isolation portion I is not necessary. The ’104 patent at14:45-56.
Notably, the ’104 patent discloses that, given the specific pattern of the first and second electrodes 140, 150, the solar cell has a bi-facial structure in which light may be incident on both surfaces of the semiconductor substrate 100. Bi-facial solar cells have improved efficiency because of the increased amount of light used in the solar cell. The ’104 patent at 16:28-35. On the other hand, the solar cell need not be limited to a bi-facial structure because the first electrode 150 can have various other structures. Id. at 16:35-39.
Finally, the ’104 patent discloses a few other embodiments that may further improve efficiency of the solar cell. For example, in a second embodiment, the ’104 patent discloses extracting metal crystals MC from the first electrode 150 and placing them in the electrode forming region 170A of the first conductive type semiconductor region 170. The ’104 patent at 18:34-38. Metal crystals MC have relatively low resistance compared to the first conductive type semiconductor region 170 made of polycrystalline silicon. As a result, they may help carriers move to the first electrode 150 more easily after moving through tunnel layer 160. Id. at 18:50-62.
The ’104 patent, Fig. 5 (coordinates repositioned, annotated).
In a third embodiment, the ’104 patent suggests placing metal crystals MC in the narrower finger forming region 170A1, but not in the wider bus bar forming region 170A2. 21:4-13. In the thermal treatment process, the metal crystals MC having a relatively great length or width may penetrate the tunnel layer 160 and may be short-circuited with the semiconductor substrate 100. The change in the third embodiment prevents such penetration and short-circuiting. Id.at 21:35-38; see also id., Fig. 8.
The ’104 patent, Fig. 9.
Claim 1 of the ’104 patent recites:
A solar cell, comprising:
a semiconductor substrate;
a tunnel layer on a first surface of the semiconductor substrate;
a first conductive type semiconductor region on the tunnel layer and containing impurities of a first conductive type;
a second conductive type semiconductor region on a second surface opposite to the first surface of the semiconductor substrate and containing impurities of a second conductive type opposite to the first conductive type;
a first passivation film on the first conductive type semiconductor region;
a first electrode formed on the first passivation film and connected to the first conductive type semiconductor region through an opening formed in the first passivation film;
a second passivation film on the second conductive type semiconductor region;
a second electrode formed on the second passivation film and connected to the second conductive type semiconductor region through an opening formed in the second passivation film; and
an isolation portion for preventing a contact between the first conductive type semiconductor region and the second conductive type semiconductor region,
wherein the isolation portion excludes the tunnel layer and the first conductive type semiconductor region, and is in an edge portion of the first surface of the semiconductor substrate, and
wherein the first passivation film covers the first surface of the semiconductor substrate and the isolation portion together.
The ’104 patent at 37:66-38:32.
The ’009 Patent
The ’009 patent is a continuation of the ’104 patent. While the ’104 patent discloses that the passivation films 190A, 190B and the anti-reflection layer 130 may include various materials, the ’009 patent additionally discloses that the passivation films 190A and 190B can also be formed of a plurality of layers. Compare the ’104 patent at 11:65-67 to the ’009 patent at 12:2-3. This addition does not change the purported invention and benefits of the ’104 patent.
Claim 1 of the ’009 patent recites:
A solar cell, comprising:
a silicon semiconductor substrate having a first conductive type;
an oxide layer on a first surface of the silicon semiconductor substrate;
a polysilicon layer on the oxide layer and having the first conductive type;
an emitter region at a second surface of the silicon semiconductor substrate opposite to the first surface and having a second conductive type opposite to the first conductive type;
a first passivation film on the polysilicon layer;
a first electrode connected to the polysilicon layer through an opening formed in the first passivation film;
a second passivation film on the emitter region;
a second electrode connected to the emitter region through an opening formed in the second passivation film; and
an isolation portion for preventing a contact between the polysilicon layer and the emitter region,
wherein the isolation portion excludes the oxide layer and the polysilicon layer, and is in an edge portion of the first surface of the silicon semiconductor substrate, and
the first passivation film covers the first surface of the silicon semiconductor substrate and the isolation portion together.
The ’009 patent at 37:65-38:25.